Merge pull request #5 from xamidev/time
1000Hz PIC timer working + IDT dispatch/handler fixes
This commit was merged in pull request #5.
This commit is contained in:
2
Makefile
2
Makefile
@@ -1,6 +1,6 @@
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build:
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rm -f *.o
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x86_64-elf-gcc -g -c -I src src/idt/idt.c src/mem/utils.c src/mem/gdt.c src/io/serial.c src/io/term.c src/io/printf.c src/kmain.c -Wall -Wextra -std=gnu99 -nostdlib -ffreestanding -fno-stack-protector -fno-stack-check -fno-PIC -ffunction-sections -fdata-sections -mcmodel=kernel
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x86_64-elf-gcc -g -c -I src src/time/timer.c src/idt/idt.c src/mem/utils.c src/mem/gdt.c src/io/serial.c src/io/term.c src/io/printf.c src/kmain.c -Wall -Wextra -std=gnu99 -nostdlib -ffreestanding -fno-stack-protector -fno-stack-check -fno-PIC -ffunction-sections -fdata-sections -mcmodel=kernel
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objcopy -O elf64-x86-64 -B i386 -I binary zap-light16.psf zap-light16.o
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nasm -f elf64 src/idt/idt.S -o idt_stub.o
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x86_64-elf-ld -o pepperk -T linker.ld *.o
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@@ -1,2 +1,3 @@
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target remote localhost:1234
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set disassembly-flavor intel
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set disassembly-flavor intel
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display/8i $rip
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135
src/idt/idt.S
135
src/idt/idt.S
@@ -34,22 +34,22 @@ interrupt_stub:
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; executed when the interrupt happened.
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; (except rsp because it will already be saved in the iret frame)
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push rax
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push rbx
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push rcx
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push rdx
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push rsi
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push rdi
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push rsp
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push rbp
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push r8
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push r9
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push r10
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push r11
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push r12
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push r13
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push r14
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push r15
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push qword rax
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push qword rbx
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push qword rcx
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push qword rdx
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push qword rsi
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push qword rdi
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;push qword rsp
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push qword rbp
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push qword r8
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push qword r9
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push qword r10
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push qword r11
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push qword r12
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push qword r13
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push qword r14
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push qword r15
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; Put stack pointer as first argument of our function
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mov rdi, rsp
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@@ -57,22 +57,22 @@ interrupt_stub:
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; What the function returns (new stack pointer) is saved in rbp
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mov rsp, rax
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pop r15
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pop r14
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pop r13
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pop r12
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pop r11
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pop r10
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pop r9
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pop r8
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pop rbp
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pop rsp
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pop rdi
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pop rsi
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pop rdx
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pop rcx
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pop rbx
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pop rax
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pop qword r15
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pop qword r14
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pop qword r13
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pop qword r12
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pop qword r11
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pop qword r10
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pop qword r9
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pop qword r8
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pop qword rbp
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;pop qword rsp
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pop qword rdi
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pop qword rsi
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pop qword rdx
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pop qword rcx
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pop qword rbx
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pop qword rax
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; Removing the error code and vector number so stack doesn't
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; get corrupted
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@@ -80,7 +80,7 @@ interrupt_stub:
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; Restore ss, rsp, rflags, cs, rip of code that was executing
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; before the interrupt
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iret
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iretq
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; Vector handlers will be 16-byte aligned so that we can loop over them
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; like <vector_no> * 16 to get each one's address
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@@ -233,4 +233,71 @@ vector_21_handler:
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push qword 21
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jmp interrupt_stub
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; The others are reserved (22->31) or external (32->255) interrupts
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; The others are reserved (22->31) or external (32->255) interrupts
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align 16
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vector_22_handler:
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push qword 0
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push qword 22
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jmp interrupt_stub
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align 16
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vector_23_handler:
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push qword 0
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push qword 23
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jmp interrupt_stub
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align 16
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vector_24_handler:
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push qword 0
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push qword 24
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jmp interrupt_stub
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align 16
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vector_25_handler:
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push qword 0
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push qword 25
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jmp interrupt_stub
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align 16
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vector_26_handler:
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push qword 0
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push qword 26
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jmp interrupt_stub
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align 16
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vector_27_handler:
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push qword 0
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push qword 27
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jmp interrupt_stub
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align 16
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vector_28_handler:
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push qword 0
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push qword 28
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jmp interrupt_stub
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align 16
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vector_29_handler:
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push qword 0
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push qword 29
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jmp interrupt_stub
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align 16
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vector_30_handler:
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push qword 0
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push qword 30
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jmp interrupt_stub
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align 16
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vector_31_handler:
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push qword 0
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push qword 31
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jmp interrupt_stub
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; PIT timer
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align 16
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vector_32_handler:
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push qword 0
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push qword 32
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jmp interrupt_stub
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@@ -9,6 +9,9 @@ struct idtr idt_reg;
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// Address to our first interrupt handler
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extern char vector_0_handler[];
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// Timer ticks
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extern uint64_t ticks;
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void idt_set_entry(uint8_t vector, void* handler, uint8_t dpl)
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{
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uint64_t handler_addr = (uint64_t)handler;
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@@ -119,6 +122,13 @@ struct cpu_status_t* interrupt_dispatch(struct cpu_status_t* context)
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serial_kputs("kernel: idt: Control Protection Exception!\n");
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break;
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case 32:
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serial_kputs("Tick!");
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ticks++;
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// Send an EOI so that we can continue having interrupts
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outb(0x20, 0x20);
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break;
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default:
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serial_kputs("kernel: idt: Unexpected interrupt\n");
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break;
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@@ -36,7 +36,7 @@ struct cpu_status_t
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uint64_t r9;
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uint64_t r8;
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uint64_t rbp;
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uint64_t rsp;
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//uint64_t rsp;
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uint64_t rdi;
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uint64_t rsi;
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uint64_t rdx;
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@@ -7,4 +7,7 @@ enum ErrorCodes
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EIO
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};
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#define CLEAR_INTERRUPTS __asm__ volatile("cli")
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#define SET_INTERRUPTS __asm__ volatile("sti")
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#endif
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21
src/kmain.c
21
src/kmain.c
@@ -7,6 +7,8 @@
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#include "mem/gdt.h"
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#include "mem/utils.h"
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#include "idt/idt.h"
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#include "kernel.h"
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#include "time/timer.h"
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// Limine version used
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__attribute__((used, section(".limine_requests")))
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@@ -36,20 +38,6 @@ static void hcf()
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}
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}
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static inline void trigger_div0(void)
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{
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asm volatile (
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"mov $1, %%rax\n"
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"xor %%rdx, %%rdx\n"
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"xor %%rcx, %%rcx\n" // divisor = 0
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"idiv %%rcx\n"
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:
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:
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: "rax", "rcx", "rdx"
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);
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}
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// This is our entry point
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void kmain()
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{
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@@ -63,12 +51,15 @@ void kmain()
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if (serial_init()) kputs("kernel: serial: error: Cannot init serial communication!");
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CLEAR_INTERRUPTS;
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gdt_init();
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idt_init();
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timer_init();
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SET_INTERRUPTS;
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// Draw something
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printf("%s, %s!", "Hello", "world");
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trigger_div0();
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//printf("%d", 4/0);
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hcf();
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}
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74
src/time/timer.c
Normal file
74
src/time/timer.c
Normal file
@@ -0,0 +1,74 @@
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#include <stdint.h>
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#include "../io/serial.h"
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/*
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For now, the timer module will be using the PIC.
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Even though it's quite old, it's still supported by newer CPUs
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and it will be precise enough for what we'll do. Also it's easier
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to implement than ACPI etc. (we may upgrade to ACPI when we're
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interested in multi-core functionnality like SMP)
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*/
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volatile uint64_t ticks = 0;
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void pic_remap()
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{
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uint8_t master_mask = inb(0x21);
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uint8_t slave_mask = inb(0xA1);
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// ICW1: start initialization
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outb(0x20, 0x11);
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outb(0xA0, 0x11);
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// ICW2: vector offsets
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outb(0x21, 0x20); // Master PIC -> 0x20
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outb(0xA1, 0x28); // Slave PIC -> 0x28
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// ICW3: tell Master about Slave at IRQ2 (0000 0100)
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outb(0x21, 0x04);
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// ICW3: tell Slave its cascade identity (0000 0010)
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outb(0xA1, 0x02);
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// ICW4: 8086 mode
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outb(0x21, 0x01);
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outb(0xA1, 0x01);
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// Restore saved masks
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outb(0x21, master_mask);
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outb(0xA1, slave_mask);
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}
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void pic_enable()
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{
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// Enabling IRQ0 (unmasking it) but not the others
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uint8_t mask = inb(0x21);
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mask &= ~(1 << 0); // Clear bit 0 (IRQ0)
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outb(0x21, mask);
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}
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/*
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Base frequency = 1.193182 MHz
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1 tick per ms (divide by 1000) = roughly 1193 Hz
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*/
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void pit_init()
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{
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uint32_t frequency = 1000; // 1 kHz
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uint32_t divisor = 1193182 / frequency;
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// Set PIT to mode 3, channel 0
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outb(0x43, 0x36); // 0x36
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// Send divisor (low byte, then high byte)
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outb(0x40, divisor & 0xFF);
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outb(0x40, (divisor >> 8) & 0xFF);
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}
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void timer_init()
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{
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// Remapping the PIC, because at startup it conflicts with
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// the reserved IRQs we have for faults/exceptions etc.
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// so we move its IRQ0 to something not reserved (32)
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pic_remap();
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pic_enable();
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pit_init();
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}
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6
src/time/timer.h
Normal file
6
src/time/timer.h
Normal file
@@ -0,0 +1,6 @@
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#ifndef TIMER_H
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#define TIMER_H
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void timer_init();
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#endif
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