IDT: set entry, load into IDTR, interrupt stub + dispatcher for common faults

src/idt/idt.S

@@ -0,0 +1,234 @@
+; Assembly stub for the IDT
+
+bits 64
+
+extern interrupt_dispatch
+
+global interrupt_stub
+global vector_0_handler
+global vector_1_handler
+global vector_2_handler
+global vector_3_handler
+global vector_4_handler
+global vector_5_handler
+global vector_6_handler
+global vector_7_handler
+global vector_8_handler
+global vector_9_handler
+global vector_10_handler
+global vector_11_handler
+global vector_12_handler
+global vector_13_handler
+global vector_14_handler
+global vector_15_handler
+global vector_16_handler
+global vector_17_handler
+global vector_18_handler
+global vector_19_handler
+global vector_20_handler
+global vector_21_handler
+
+interrupt_stub:
+    ; We'll push all general-purpose registers to the stack,
+    ; so they're intact and don't bother the code that was
+    ; executed when the interrupt happened.
+    ; (except rsp because it will already be saved in the iret frame)
+    
+    push rax
+    push rbx
+    push rcx
+    push rdx
+    push rsi 
+    push rdi
+    push rbp
+    push r8
+    push r9
+    push r10
+    push r11
+    push r12
+    push r13
+    push r14
+    push r15
+
+    ; Put stack pointer as first argument of our function
+    mov rdi, rsp
+    call interrupt_dispatch
+    ; What the function returns (new stack pointer) is saved in rbp
+    mov rsp, rax
+
+    pop r15
+    pop r14
+    pop r13
+    pop r12
+    pop r11
+    pop r10
+    pop r9
+    pop r8
+    pop rbp
+    pop rdi
+    pop rsi
+    pop rdx
+    pop rcx
+    pop rbx
+    pop rax
+
+    ; Removing the error code and vector number so stack doesn't
+    ; get corrupted
+    add rsp, 16
+    
+    ; Restore ss, rsp, rflags, cs, rip of code that was executing
+    ; before the interrupt
+    iret
+
+; Vector handlers will be 16-byte aligned so that we can loop over them
+; like <vector_no> * 16 to get each one's address
+
+; Divide Error
+align 16
+vector_0_handler:
+    ; error code (nothing, so we push a dummy 0 quadword, 64bits/8bytes long)
+    push qword 0
+    ; vector number (so our interrupt stub knows which one it is)
+    push qword 0
+    jmp interrupt_stub
+
+; Debug Exception
+align 16
+vector_1_handler:
+    push qword 0
+    push qword 1
+    jmp interrupt_stub
+
+; NMI
+align 16
+vector_2_handler:
+    push qword 0
+    push qword 2
+    jmp interrupt_stub
+
+; Breakpoint
+align 16
+vector_3_handler:
+    push qword 0
+    push qword 3
+    jmp interrupt_stub
+
+; Overflow
+align 16
+vector_4_handler:
+    push qword 0
+    push qword 4
+    jmp interrupt_stub
+
+; BOUND Range exceeded
+align 16
+vector_5_handler:
+    push qword 0
+    push qword 5
+    jmp interrupt_stub
+
+; Invalid Opcode
+align 16
+vector_6_handler:
+    push qword 0
+    push qword 6
+    jmp interrupt_stub
+
+; Device Not Available
+align 16
+vector_7_handler:
+    push qword 0
+    push qword 7
+    jmp interrupt_stub
+
+; Double Fault
+align 16
+vector_8_handler:
+    ; No error code, we only push vector number
+    push qword 1
+    jmp interrupt_stub
+
+; Coprocessor Segment Overrun
+align 16
+vector_9_handler:
+    push qword 9
+    jmp interrupt_stub
+
+; Invalid TSS
+align 16
+vector_10_handler:
+    push qword 10
+    jmp interrupt_stub
+
+; Segment Not Present
+align 16
+vector_11_handler:
+    push qword 11
+    jmp interrupt_stub
+
+; Stack-Segment Fault
+align 16
+vector_12_handler:
+    push qword 12
+    jmp interrupt_stub
+
+; General Protection
+align 16
+vector_13_handler:
+    push qword 13
+    jmp interrupt_stub
+
+; Page Fault
+align 16
+vector_14_handler:
+    push qword 14
+    jmp interrupt_stub
+
+; Intel reserved
+align 16
+vector_15_handler:
+    push qword 0
+    push qword 15
+    jmp interrupt_stub
+
+; x87 FPU Floating-Point Error
+align 16
+vector_16_handler:
+    push qword 0
+    push qword 16
+    jmp interrupt_stub
+
+; Alignment Check
+align 16
+vector_17_handler:
+    push qword 17
+    jmp interrupt_stub
+
+; Machine Check
+align 16
+vector_18_handler:
+    push qword 0
+    push qword 18
+    jmp interrupt_stub
+
+; SIMD Floating-Point Exception
+align 16
+vector_19_handler:
+    push qword 0
+    push qword 19
+    jmp interrupt_stub
+
+; Virtualization Exception
+align 16
+vector_20_handler:
+    push qword 0
+    push qword 20
+    jmp interrupt_stub
+
+; Control Protection Exception
+align 16
+vector_21_handler:
+    push qword 21
+    jmp interrupt_stub
+
+; The others are reserved (22->31) or external (32->255) interrupts